(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to the etching of contact openings in the manufacture of sub-micron MOSFETs.
(2) Background of the Invention and Description of Prior Art
The fabrication of integrated circuit chips comprises the formation of semiconductor devices within the surface of a single crystalline silicon wafer. The semiconductive elements of metal-oxide-silicon-field-effect-transistors (MOSFETs) are contained within the surface of the single crystalline substrate wafer and are formed by ion-implantation using the control electrode, a polysilicon gate formed over the substrate, as an implantation mask. The source and drain regions of the MOSFET are thereby self-aligned to the gate electrode.
Many variations of the principle of self alignment to the polysilicon gate have been developed to improve device performance and stability, in particular, the use of side walls along the edges of the polysilicon gate have permitted the tailoring of source and drain diffusions at the ends of the channel region to control short channel effects. These advances in MOSFET processing have resulted in high performance sub-micron sized devices of many types. The lightly-doped-drain (LDD) structure, used universally in sub-micron MOSFET technology, is a notable example of this side-wall tailoring.
The use of insulative sidewalls and caps over polysilicon conductors has also permitted the formation of self-aligned contacts (SAC) to MOSFET active elements. Self-alignment processing utilizes reactive-ion-etching (RIE) to anisotropically etch vertical walled openings, typically through insulative layers, such as silicon oxide and various silicate glasses.
Self-aligned-contacts can be made in various configurations. Typically an insulative sidewall is provided along the edge of the polysilicon gate electrode. The sidewall provides an insulative spacing between the contact and the polysilicon gate. Referring to FIG. 1 there is shown a cross section of a silicon wafer with two adjacent MOSFETs. The configuration shown here is typical of a well known design (DASH Cell) for a dynamic random access memory(DRAM) cell. The polysilicon gate electrodes 18 form the wordlines of the DRAM. The source/drain diffusions 12, 14 are formed by the widely used LDD process utilizing the sidewalls 27. In subsequent processing steps, storage capacitors are formed over the semiconductive elements 14 while a bitline contact is made to the semiconductive element 12.
The polysilicon wordlines in this example have a tungsten silicide layer 20 and a thin silicon oxide layer 22 over them. The sidewalls 27 and a top protective layer 24 are formed of silicon nitride. These layers are formed and patterned by conventional modern processing techniques well known to those in the art. An insulative layer 26 of silicon oxide is deposited over the wafer 10 followed by a silicate glass layer 28, for example, phosphosilicate glass PSG or borophosphosilicate glass(BPSG). This layer 28 is planarized by any of several well known techniques, for example chemical mechanical polishing (CMP). An opening for the bitline contact is then defined using well known photolithographic processing methods, whereby a pattern is formed in a photoresist layer 30. The photomask opening 32 can be made larger than the contact area at the silicon surface. The self-alignment feature also permits slight mis-alignment of the photomask because the contact at the silicon is determined by the nitride sidewall 27.
The wafer 10 is next subjected to an RIE processing step whereby the opening 32 for the bitline contact is etched through the insulative layers 26, 28. The etchant gas and the RIE parameters are selected to provide vertical walls in the opening in the silicon oxide layer and a high silicon oxide etch rate selectivity, that is to say, a high silicon oxide/silicon nitride etch rate ratio. The opening 32 illustrated in FIG. 2 was formed with an etch rate sensitivity sufficiently high that the nitride sidewalls 27 and the exposed upper portions of the nitride top cap 24 were imperceptibly etched. The layer 36 is a polymer which is formed during the etching process. Under conditions of inadequate etch rate selectivities the nitride sidewalls 27 and top nitride cap 24 etch at rates whereby the insulative spacing provided by these elements is reduced by erosion of the nitride, resulting in subsequent shorts between bitline and wordline. This is illustrated in FIG. 3 Where the upper corners 34 of the wordlines have been exposed.
Until recently, etch rate selectivities greater than about 8:1 were not attainable without sacrificing other important aspects such as etching anisotropy. In the current technology, where dimensional features are of the order of quarter micron, it becomes increasingly more difficult to achieve a sufficiently high etch rate selectivity for this contact opening etch without aggravating deleterious side effects, for example incomplete oxide removal at the base of the contact resulting in unacceptable contact resistance.
Marks, et.al., U.S. Pat. No. 5,423,945 discloses reducing the fluorine content of the passivation polymer, and reducing the amount of free fluorine in the plasma, reduces the dissociation of the polymer. By adding a fluorine scavenger such as silicon or carbon ions to the plasma, the resultant polymer becomes carbon rich and is more resistant to dissociation. In an example, an etch rate selectivity of oxide to nitride of 15:1 was achieved by the use of a fluorine scavenger.
Yanagida, et.al., U.S. Pat. No. 5,338,399 obtain high etch rate selectivities of insulators with respect to silicon base material, while also achieving low pollution, and low silicon damage, by using cyclic fluorocarbons, for example octafluorocyclobutane (C.sub.4 F.sub.8) to etch contact openings. The cyclic fluorocarbons provide a higher C/F ratio than comparable straight chain fluorocarbons which is considered beneficial for effectively depositing carbonaceous polymers.
It is widely believed that polymer formation in an RIE plasma containing fluorocarbon etchants, is largely responsible, not only for the etching anisotropy, but also for the etch rate selectivity. In the case of silicon oxide etching, the polymer formed at the etching front is rapidly dissociated by the released oxygen. However, over regions of silicon nitride, the oxygen concentration is less and the polymer is not readily dissociated, thereby providing passivation of the silicon nitride.
In order to achieve the high etch rate sensitivity to achieve the profile shown in FIG. 2, it was necessary to utilize etchant gases and RIE parameters which provided a relatively high steady state polymer thickness over the Si.sub.3 N.sub.4. The residual polymer 36 is shown prior to its removal at the termination of the etching operation. An insufficient steady state polymer thickness leads to the profile shown in FIG. 3. where the Si.sub.3 N.sub.4 has been eroded.
As device densities are increased and their geometries become smaller, new problems arise in the etching of openings for self-aligned contacts. In particular, as the dimensions of the contact openings enter the sub-quarter micron range, difficulties are encountered with clearing of insulative material from the base of the opening when etching at high SiO.sub.2 /Si.sub.3 N.sub.4 selectivities. Heavy polymer formation over the silicon nitride spacers interferes with the proper clearance of insulative material at the base of the opening by bridging across the narrow opening, thereby terminating the etching. Residual oxide in the opening causes opens or unacceptably high contact resistance.
FIG. 4A illustrates a cross section of a bitline contact opening 40 defined by a photoresist masking layer 30. The layout is similar to that shown in FIG. 1 except that now the spacing between the polysilicon wordlines is reduced. The width d, of the photoresist opening 40 which defines the upper part of the SAC is between about 0.25 and 0.3 .mu.m. However, the distance d.sub.2 between the silicon nitride spacers 27 at the base of the SAC opening is about 0.15 .mu.m or less.
FIG. 4B shows the contact cross section at an instant during the etching when the etch front has traveled through the upper portion of the silicate glass layer 28 and has just penetrated the silicon oxide layer 26. When the etch front penetrates the silicon oxide layer 26 as shown in FIG. 4B, the rate of polymer formation on the exposed oxide layer 26 is different than that over the central remaining portion 28A of the silicate glass layer 28 causing a topographic irregularity at the SiO.sub.2 /Glass interface. The silicate glass 28A etches at rate about 10% slower than the SiO.sub.2 layer 16. Then, referring to FIG. 4C, as the etch front proceeds further to expose the Si.sub.3 N.sub.4 caps 24 and the Si.sub.3 N.sub.4 sidewall structures 27, a polymer layer 36 forms over the Si.sub.3 N.sub.4 structures.
Eventually, as the opening narrows between the Si.sub.3 N.sub.4 sidewalls 27, the thick polymer over the Si.sub.3 N.sub.4 bridges the opening and pinches off access of the reactant gases to the underlying oxide /silicate glass 38, resulting in incomplete clearance at the SAC base. This is shown in the cross section in FIG. 4D. The residual material 38 in the opening may cause an open or unacceptable and erratic high resistance contacts.
Dunfield, U.S. Pat. No. 4,793,897 shows a plasma process using a fluorinated etching gas mixture with oxygen to selectively etch silicon nitride with high selectivity for an underlying silicon oxide layer. The mixture contains NF.sub.3, SiF.sub.4 and O.sub.2. The NF.sub.3 is the main nitride etchant while the O.sub.2 combines with silicon from the SiF.sub.4 to selectively form a silicon oxide containing deposit on the oxide underlayer and thus increase the selectivity for oxide layers. Thornquist, U.S. Pat. No. 4,568,410 also shows a method for etching Si.sub.3 N.sub.4 in the presence of SiO.sub.2 using a gas including NF.sub.3.